Microchip SY58020U manual

Microchip SY58020U
9.6 · 1
PDF user manual
 · 13 pages
English
user manualMicrochip SY58020U

SY58020U

6GHz, 1:4 CML Fanout Buffer/Translator

with Internal I/O Termination

Precision Edge is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 27
, 2014
Revision 5.0
tcghelp@micrel.com or (408) 955-1690

General Description

The SY58020U is a 2.5V/3.3V precision, high-speed, fully
differential 1:4 CML fanout buffer. Optimized to provide
four identical output copies with less than 15ps of skew
and 27fs
RMS
of typical additive phase jitter, the SY58020U
can process clock signals as fast as 6GHz.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that interfaces to differential
LVPECL, LVDS, and CML signals (AC- or DC-coupled) as
small as 100mV without any level-shifting or termination
resistor networks in the signal path. For AC-coupled input
interface applications, an on-board output reference
voltage (V
REF-AC
) is provided to bias the V
T
pin. The outputs
are optimized to drive 400mV typical swing into 50 loads,
with extremely fast rise/fall times guaranteed to be less
than 60ps.
The SY58020U operates from a 2.5V ±5% supply or 3.3V
±10% supply and is guaranteed over the full industrial
temperature range (40°C to +85°C). For applications that
require LVPECL outputs, consider the SY58021U or
SY58022U 1:4 fanout buffer with 800mV and 400mV
output swing, respectively. The SY58020U is part of
Micrel’s high-speed, Precision Edge
®
product line.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com
.

Features

Precision 1:4, 400mV CML fanout buffer
Guaranteed AC performance over temperature/voltage:
> 6GHz f
MAX
clock
< 60ps t
r
/ t
f
times
< 250ps t
pd
<
15ps max. skew
Low-jitter performance:
27fs
RMS
typical additive phase jitter
Accepts an input signal as low as 100mV
Unique patented input termination and V
T
pin accepts
DC-coupled and AC-coupled differential inputs:
LVPECL, LVDS, and CML
50 source terminated CML outputs
Power supply 2.5V ±5% and 3.3V ±10%
Industrial temperature range: 40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN pack
age

Applications

All SONET and All GigE clock distribution
Fibre Channel clock and data distribution
Backplane distribution
Data distribution: OC-48, OC-48+FEC, XAUI
High-end, low skew, multiprocessor synchronous clock
distribution

Functional Block Diagram Typical Performance

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